A Novel Multi-Bit Parallel ΔΣ FM-to-Digital Converter with 24-bit Resolution

摘要

This paper describes a multi-bit ΔΣ FM-to-digitalrnconverter (FDC) combining 1024 first-order ΔΣ modulatorsrnin parallel to increase the signal to quantization-noisernratio (SQNR). This parallelization technique is totally newrnand according to theory, the SQNR is increased by 6 dBrnper doubling of number of modulators. The proposed circuitrnis an extension of the existing frequency delta sigmarnmodulator (FDSM)-concept. The FDSM-concept is basedrnon a ΔΣ-modulator with no global feedback and thus nornneed for a feedback DAC, which makes multi-bit conversionrnstraight forward. Theoretical discussions and circuitrnsimulation are presented along with measured results fromrna 24-bit parallel FDC which has been implemented in arnstandard 0.6um CMOS process from Austria Micro SystemernAG (AMS). For a 150 Hz bandwidth the measuredrnSQNR is 146 dB with a clock frequency of 20 MHz.