MDAC Design for an 8-bit 40 MS/s Pipelined ADC in a 0.18μm CMOS Process

摘要

This paper presents an MDAC (Multiplying Digital-to-Analog Converter) for a low power eight bit and 40-MS/s pipeline ADC (Analog-to-Digital converter). The operational amplifier (Op-Amp) dedicated fir this type of converters is performed by using telescopic architecture that has the advantages of low power and less-area. In addition to the reducing of area and power the MDAC is designed using multifunction 1.5 bit/stage architecture.