Reconfigurable channel filtering architecture based on two bit sub expression minimization for digital up conversion in Software Defined Radio

摘要

A low power and low area reconfigurable architecture implying a square root raised cosine (SQRRC) interpolation filter for multi-standard Software-defined radio (SDR) is presented in this paper. The inception of the SDR technology has inspired one to attempt to develop a single device which is capable of supporting multiple wireless communication standards. To support multiple standard wireless protocols such as WCDMA, UMTS and DVB in a single device, a reconfigurable root raised cosine filter is needed due to its property to sample at low Bit Error Ratio (BER). Hence filters with taps 25, 37 and 49 with interpolation factors of 4,6 and 8 respectively based on the communication standards mentioned above with two different roll-off factors has been implemented. A two-bit Binary Subexpression elimination algorithm has been used to design an efficient multiple constant multiplier. In the proposed work, the coefficients are pre stored to reduce the excessive switching activities and the addition blocks are restructured using a parallel approach to reduce logic depth. The results show that the proposed architecture consumes less power and occupies smaller area compared to the existing architectures.