Scalable security path methodology: A cost-security trade-off to protect FPGA IPs against active and passive tampers

摘要

Modern FPGAs have a great market share in the hardware design industry and are used as primary elements in different critical applications like aerospace, automotive, military etc. They also are widely used in hardware prototyping, massive parallel systems and reconfigurable architectures. Short time to market and flexibility are two good features of FPGAs in the growth and diversity of their applications. However, field programmability has caused security concerns for IPs/Designs on FPGAs. Research shows that a reliable mechanism is required to protect the IPs/applications on FPGAs against malicious manipulations during all stages of design lifecycle, especially when they are operating in the field. In this paper, we propose a new tamper-resistant design methodology (Security Path methodology) and a revised security-aware FPGA architecture to protect the design against tampering attacks in parallel with the normal operation of the circuit. CAD tool is also updated to analyze vulnerabilities of the design and automatically insert the security modules inside the target generated IPs. All these proceedings are implemented with a balance approach between implementation costs and required security level.