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Study of 25nm Symmetric Extended Source/Drain Schottky Tunneling Transistors

机译:25nm对称扩展源/漏肖特基隧道晶体管的研究

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摘要

The performance of 25nm Symmetric Extended Source/Drain Schottky Tunneling Transistor (ESD-ST-SOIFET) with different gate structures are investigated through a TCAD modeling study. It is shown that, the doped extension regions adjacent to the source/drain schottky barrier improves the drive current by shrinking the schottky barrier and also the simulation results shows that the increasing doping levels at the source/drain(S/D) extensions increases the leakage current. The device shows better short channel effects compared to other schottky barrier devices. The analysis also shows that, the best characteristics of the proposed device can be obtained only if using proper silicides at the S/D regions. For best performance platinum silicide can be used for p-type and Erbium silicide can be used for n-type devices.
机译:通过TCAD建模研究,研究了具有不同栅极结构的25nm对称扩展源极/漏极肖特基隧穿晶体管(ESD-ST-SOIFET)的性能。结果表明,与源极/漏极肖特基势垒相邻的掺杂延伸区通过收缩肖特基势垒来改善驱动电流,并且仿真结果表明,源极/漏极(S / D)延伸区掺杂水平的提高会增加漏电流。与其他肖特基势垒器件相比,该器件显示出更好的短沟道效应。分析还表明,只有在S / D区域使用适当的硅化物时,才能获得所提出器件的最佳特性。为了获得最佳性能,硅化铂可用于p型,硅化icide可用于n型器件。

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