Time Warp synchronized parallel discrete event simulators are organized to operate asynchronously and aggressively without explicit synchronization between the concurrently executing simulators. In place of an explicit synchronization mechanism, the concurrent simulators maintain a common virtual clock model and implement a rollback/recovery mechanism to restore causal order when out-of-order events are detected. When the critical path of execution of the simulation is balanced across these parallel simulators, this can result in a highly effective, lightweight synchronization mechanism. However, imbalances in the workload across the parallel simulators can result in excessive rollback at some nodes and ultimately result in an overall slowing of the simulation as prematurely computed and transmitted events are processed. On small shared memory multi-core systems, a lowest time-stamp first scheduling policy can effectively balance the workload. However, on larger many-core chips, conventional load balancing and workload migration will once again become necessary. Fortunately, emerging many-core chips contain some interesting features that can potentially be exploited to improve the performance of parallel simulations. For example, the Intel Single-chip Cloud Computer (SCC) provides mechanisms that a running application can use to adjust the frequency/voltage of different regions (called islands) of the chip. These islands are network and processing core centric and thus, in a Time Warp simulation, one can increase the frequency of the cores executing threads on the critical path (those experiencing infrequent rollback) and decrease the frequency of the cores executing threads off the critical path (those experiencing excessive rollback). This paper investigates the run-time control and adjustment of core frequency in an AMD Phenom II X6 multi-core processor to explore and demonstrate that the dynamic run-time control of core frequency can sometimes improve the perfo- mance of a Time Warp synchronized parallel simulation.
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机译：时间扭曲同步并行离散事件模拟器经过组织，可以异步且积极地运行，而同时执行的模拟器之间无需显式同步。代替显式同步机制，并发模拟器维护一个公共的虚拟时钟模型并实现回滚/恢复机制，以在检测到乱序事件时恢复因果关系。当在这些并行仿真器之间平衡仿真执行的关键路径时，这可以形成一种高效，轻便的同步机制。但是，跨并行模拟器的工作负载不平衡可能会导致某些节点上的过度回滚，并最终导致在处理过早计算和传输的事件时使模拟总体变慢。在小型共享内存多核系统上，最低的时间戳优先调度策略可以有效地平衡工作负载。但是，在更大的多核芯片上，传统的负载平衡和工作负载迁移将再次成为必需。幸运的是，新兴的多核芯片包含一些有趣的功能，可以潜在地利用这些功能来提高并行仿真的性能。例如，英特尔单芯片云计算机（SCC）提供了运行中的应用程序可用来调整芯片不同区域（称为岛）的频率/电压的机制。这些孤岛以网络和处理核心为中心，因此，在“时间扭曲”仿真中，可以增加在关键路径上执行线程的核心的频率（经历很少回滚的频率），并降低在关键路径上执行线程的核心的频率（经历过多回滚的用户）。本文研究了AMD Phenom II X6多核处理器中的运行时控制和核心频率的调整，以探索并证明动态运行时控制核心频率有时可以提高Time Warp同步并行系统的性能。模拟。
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