Fabrication and Transport Behavior Investigation of Gate-Ail-Around Silicon Nanowire Transistor from Top-Down Approach (invited)

摘要

Gate-all-around silicon nanowire transistor (SNWT) can be considered as the good candidate for highly scaled devices to the end of roadmap. This paper mainly discusses a new process integration scheme proposed by us, which features bulk substrate based, cpi-frcc integration, self-aligned structure and large source/drain fan-out. The characteristics of the fabricated device with 10nm diameter nanowire were investigated. The transport behavior of the SNWTs is experimentally estimated, with a modified experimental extraction methodology for SNWTs given, which takes into account the impact of temperature dependence of parasitic source resistance in the SNWTs with quasi-1D channel structure. The sub-40nm SNWTs exhibit high ballistic efficiency at room temperature, indicating the great potentials of SNWTs as an alternative device structure for near-ballistic transport. Sclf-hcating effect is also experimentally characterized and due to the 1-D nature of nanowire and increased phonon-boundary scattering in GAA structure, the sclf-hcating effect in SNWTs based on bulk substrate is comparable or even a little bit worse than SOI devices, which may limit the ultimate performance of SNWT-based circuits and thus special design consideration is expected.