CMP Pad Design for Ultra-low K Compatible Cu CMP Process

摘要

CMP is an enabling process technology for advanced sub-micron integration using copper damascene. Copper CMP process must meet increasingly stringent requirements for metal loss. ITRS 2005 suggests a total metal loss budget (at 10% of total metal) of 120 A at 65 nm, which reduces to 60A for the 32nm node. ITRS roadmap also suggests potential simultaneous incorporation of low-k dielectric, which will likely be porous. Novel dielectrics and their stacking are susceptible to cohesive and adhesive failures, when processed under conditions, which are optimized for conventional dielectrics. Consequently, low-k process integration must include a planarization technology, which offers low mechanical impact to the target materials. Additionally, process must offer the ability to process wafers with minimal over-polish to achieve metal loss and defectivity targets.