On the Tracking Performance of a Galileo/GPSReceiver Based on Hybrid FPGA/DSP Board

摘要

The design of receivers in the field of Global NavigationrnSatellite Systems (GNSS) is going through a fundamentalrnstage of development. As a matter of fact, the market isrnshowing the need of having user terminals with improvedrnperformance, and able to match the requirements ofrndifferent services and applications related to positioning.rnOn the other hand, the constant advancements on the wayrnleading to the modernization of the actual GlobalrnPositioning System (GPS) and the development of the new European Satellite System, Galileo, are driving the designrnof new architectures for the future GNSS receivers able tornmanage signals with high sampling rates.rnConsidering this framework, the solution of developingrnsuch user terminals on reconfigurable platforms has grownrnin importance. From the manufacturers point of view,rnsuch an approach will make possible to upgrade andrnreconfigure the system with new features, while from thernresearch point of view it will make easier to perform testsrnon signal processing algorithms for the new modulationrnschemes foreseen by the future GNSS signalrnrequirements.rnIn this light, this paper introduces a work for thernrealization of a test receiver based on FieldrnProgrammable Gate Arrays (FPGAs) and Digital SignalrnProcessors (DSPs), design according to the SoftwarernDefined Radio (SDR) philosophy. The test receiver assurerna 100% level of flexibility for each one of its functionalrnblocks. Starting from the justification for the hardwarerntools selected, the paper reports the last results about thernanalysis of the system performance going through therndetails of the architecture description, focusing thernattention on the Code and Carrier Tracking Loops. Sincernthe new Galileo modulated Signals-In-Space (SIS) are notrnyet available, a software version of an input signalrngenerator has been realised, and its realization will berndiscussed taking care of the real-time constraints.rnResults of the Tracking Jitter Error (THE) for variousrnmodulation schemes implemented on the describedrnarchitecture are presented, comparing them withrnsimulative results.