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Fast multiplierless architecture for general purpose VLSI FIR digital filters with minimized hardware
Fast multiplierless architecture for general purpose VLSI FIR digital filters with minimized hardware
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机译:用于通用VLSI FIR数字滤波器的快速无乘法器架构,具有最少的硬件
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摘要
A digital transversal filter which employs a multiplierless algorithm for effecting convolutions of samples of a digital input word by the filter coefficients. Each of the samples of an input word is bit sliced into segments of two or more bits, and convolutions are carried out in parallel on all segments using only adders and registers. The convolution products are then summed in a pipeline adder tree to derive the convolution of the complete input word. This architecture provides high frequency capability and significantly lower transistor count and hardware complexity, enabling efficient very large scale integration (VLSI) implementation.
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