PURPOSE: To prevent a pass with strict delay constraint from running counter to delay constraint due to change when rough wiring processing is performed or detail wiring processing. ;CONSTITUTION: A delay analysis means 3 performs delay analysis with respect to each pass by using the delay value of a wiring layer with the maximum delay value and the virtual wiring length of each net. A contravention net extraction means 4 extracts the pass contravening to the delay constraint in the delay analysis, and finds the net comprising the pass. An optimum delay value wiring layer extraction means 5 finds a wiring layer which satisfies the delay constraint in the delay analysis under a virtual wiring length condition by the pass extracted by the contravention net extraction means 4. A contravention net rough wiring processing means 6 finds a rough route in which the length of the net found by the contravention net extraction means 4 can be equivalent to the virtual wiring length, and allocates the rough route to the wiring layer extracted by the optimum delay value wiring layer extraction means 5, and sets the rough route as a fixed one.;COPYRIGHT: (C)1993,JPO&Japio
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