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Redundant circuit for memory having redundant block operatively connected to special one of normal blocks

机译:具有冗余块的存储器冗余电路,该冗余块可操作地连接至普通块中的特殊块

摘要

A redundant circuit for a memory circuit having a plurality of memory cell blocks, which includes a redundant memory cell block for a predetermined one of the memory cell blocks. There is a redundancy decoder for producing a redundant memory cell selecting signal, and a block selecting signal generating circuit. The output of the block selecting signal generating circuit is arranged to be controlled by the redundant memory cell selecting signal for the predetermined memory cell block so as to relieve a faulty memory cell block by the redundant memory cell block of the predetermined memory cell block.
机译:一种用于具有多个存储单元块的存储电路的冗余电路,该冗余电路包括用于预定的一个存储单元块的冗余存储单元块。存在用于产生冗余存储单元选择信号的冗余解码器,以及块选择信号生成电路。块选择信号发生电路的输出被安排为由用于预定存储单元块的冗余存储单元选择信号控制,以便通过预定存储单元块的冗余存储单元块来减轻故障存储单元块。

著录项

  • 公开/公告号US5426607A

    专利类型

  • 公开/公告日1995-06-20

    原文格式PDF

  • 申请/专利权人 SHARP KABUSHIKI KAISHA;

    申请/专利号US19930091732

  • 发明设计人 KENJI ISHIBASHI;

    申请日1993-07-14

  • 分类号G11C7/00;G11C29/00;

  • 国家 US

  • 入库时间 2022-08-22 04:04:47

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