Asynchronous digital system, asynchronous data path circuit, asynchronous digital signal processing circuit and asynchronous digital signal processing method

摘要

An asynchronous digital system, an asynchronous data path circuit, an asynchronous digital signal processing circuit and an synchronous digital signal processing method, which enables improved processing speed while maintaining high reliability are provided by dividing the overall chip into blocks with a specified area, forming the connection between the blocks by applying thereto a delay insensitive (DI) model or a quasi delay insensitive (QDI) model, while forming each block by applying thereto a scalable delay insensitive (SDI) model. In the SDI model, the system is configured using circuit components having a delay assumed during design in which if the specification states that a signal transition (b) in a subcircuit 7 precedes a signal transition (c) in a subcircuit 8, k·Tab Tac is established wherein Tab is the time from the occurrence of the signal transition (a) that is a common cause until the occurrence of the signal transition (b) and Tac is the time from the occurrence of the signal transition (a) until the occurrence of the signal transition (c). k is a constant that is defined to be a real number larger than 1.