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Methods of forming shallow trench isolation regions using plasma deposition techniques

机译:使用等离子体沉积技术形成浅沟槽隔离区的方法

摘要

Methods of forming trench isolation regions include the steps of forming a trench in a semiconductor substrate having a surface thereon and then depositing an electrically insulating layer on the semiconductor substrate, to fill the trench. This depositing step is preferably performed by depositing an electrically insulating layer (e.g. , SiO.sub. 2) using a plasma chemical vapor. A mask layer is then formed on the electrically insulating layer. According to a preferred aspect of the present invention, the mask layer is planarized using chemical mechanical polishing, for example, to define a mask having openings therein that expose first portions of the electrically insulating layer extending opposite the surface. These first portions are also self- aligned to and extend opposite active portions of the substrate. The exposed portions of the electrically insulating layer are then etched using the mask as an etching mask. Then, the mask and second portions of the electrically insulating layer extending opposite the mask, are etched in sequence to define an electrically insulating region in the trench. This latter etching step is preferably not performed using a chemical mechanical polishing step to limit the likelihood of isolation deterioration caused by the dishing phenomenon.
机译:形成沟槽隔离区域的方法包括以下步骤:在其上具有表面的半导体衬底中形成沟槽,然后在半导体衬底上沉积电绝缘层以填充沟槽。该沉积步骤优选通过使用等离子体化学蒸气沉积电绝缘层(例如,SiO 2)来进行。然后在电绝缘层上形成掩模层。根据本发明的一个优选方面,使用化学机械抛光来对掩模层进行平坦化,例如,以限定其中具有开口的掩模,该开口暴露出与表面相对地延伸的电绝缘层的第一部分。这些第一部分也自对准并延伸到基板的相对的有源部分。然后,使用掩模作为蚀刻掩模来蚀刻电绝缘层的暴露部分。然后,依次蚀刻掩模和与掩模相对延伸的电绝缘层的第二部分,以在沟槽中限定电绝缘区域。优选地,不使用化学机械抛光步骤来执行后面的蚀刻步骤,以限制由凹陷现象引起的隔离劣化的可能性。

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