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Methods of forming trench isolation regions using preferred stress relieving layers and techniques to inhibit the occurrence of voids

机译:使用首选的应力消除层形成沟槽隔离区的方法和抑制空隙发生的技术

摘要

Methods of forming trench isolation regions include the steps of forming a trench in a semiconductor substrate and lining the trench with a first electrically insulating layer. A stress-relief nitride layer is then formed on the first electrically insulating layer, opposite sidewalls of the trench. The trench is then filled with a second electrically insulating layer. The second electrically insulating layer is then planarized. This is followed by the steps of etching the stress-relief nitride layer and then forming a third electrically insulating layer on the planarized second electrically insulating layer and on the stress-relief nitride layer. The step of forming the trench is preferably preceded by the step of forming a patterned pad nitride layer on the semiconductor substrate. The pad nitride layer may be used as a mask when etching the substrate to define the trench. The step of planarizing the second electrically insulating layer may also comprise the step of planarizing the second electrically insulating layer using the patterned pad nitride layer as an etch stop.
机译:形成沟槽隔离区的方法包括以下步骤:在半导体衬底中形成沟槽,并用第一电绝缘层衬里该沟槽。然后在沟槽的相对侧壁上的第一电绝缘层上形成应力消除氮化物层。然后用第二电绝缘层填充沟槽。然后将第二电绝缘层平坦化。随后是蚀刻应力消除氮化物层,然后在平坦化的第二电绝缘层上和应力消除氮化物层上形成第三电绝缘层的步骤。优选在形成沟槽的步骤之前是在半导体衬底上形成图案化的垫氮化物层的步骤。当蚀刻衬底以限定沟槽时,垫氮化物层可以用作掩模。平坦化第二电绝缘层的步骤还可包括使用图案化的垫氮化物层作为蚀刻停止层来平坦化第二电绝缘层的步骤。

著录项

  • 公开/公告号US6187651B1

    专利类型

  • 公开/公告日2001-02-13

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号US19990306496

  • 发明设计人 YONG-CHUL OH;

    申请日1999-05-06

  • 分类号H01L217/60;

  • 国家 US

  • 入库时间 2022-08-22 01:05:13

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