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Graphic representation of circuit analysis for circuit design and timing performance evaluation
Graphic representation of circuit analysis for circuit design and timing performance evaluation
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机译:电路分析的图形表示,用于电路设计和时序性能评估
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摘要
A method and apparatus that displays a delay chart on a display screen, using a variety of user-selected formats and representing delays of a circuit being debugged. These formats include right-to-left and left-to-right displays. The displays can optionally have duplicative paths merged and zero delay paths removed. The invention also allows the designer to select various parts of the delay chart and then automatically highlights related portions of HDL code for the circuit (which also is displayed on the display screen). Conversely, the designer can select portions of the HDL code and the invention will automatically highlight related portions of the delay chart. Thus, the designer can easily determine which parts of the HDL caused large delays in the circuit being designed and can easily change those parts of the HDL in an attempt to obtain more desirable timing.
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