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STATIC DELAY ANALYSIS PROCESSING METHOD, STATIC DELAY ANALYSIS PROCESSING PROGRAM RECORD MEDIUM AND STATIC DELAY ANALYSIS PROCESSING PROGRAM

机译:静态延迟分析处理方法,静态延迟分析处理程序记录介质和静态延迟分析处理程序

摘要

PROBLEM TO BE SOLVED: To suppress a sharp increase in processing time of a static delay analysis for a circuit while making it possible to perform an exact delay calculation.;SOLUTION: A group of a pair of time and slew comprising the pair of arrival time and the slew for an output signal of each node is calculated in a topological sequence from an external input end and the group of the pair of the time and the slew in the input signal of an ensuing node is calculated from the group of the pair of the time and the slew of its output signal. A plural pairs of the time and the slew in every input or output of the each node is saved as such, and the timing analysis is executed based on the pair of the time and the slew. And, execution time of the delay analysis can be reduced by deleting the pair of the time and the slew in the group of the pairs of the time and the slew in the input or output of the each node which does not affect the delay analysis or does it to a small extent.;COPYRIGHT: (C)2002,JPO
机译:解决的问题:抑制电路的静态延迟分析的处理时间急剧增加,同时使执行精确的延迟计算成为可能。;解决方案:一对时间和压摆组成的一组,包括一对到达时间并且从外部输入端按照拓扑顺序计算每个节点的输出信号的摆率,并从该对的时间对中计算出该对时间的组,随后的节点的输入信号中的对摆率时间及其输出信号的摆率。这样保存每个节点的每个输入或输出中的多对时间和回转,并基于该对时间和回转执行时序分析。并且,可以通过删除不影响延迟分析或每个节点的输入和输出的时间对的对的组中的一对时间和转换,来减少延迟分析的执行时间。做到这一点的程度很小。;版权所有:(C)2002,日本特许厅

著录项

  • 公开/公告号JP2002251425A

    专利类型

  • 公开/公告日2002-09-06

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP20010381057

  • 发明设计人 TAMIYA YUTAKA;

    申请日2001-12-14

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-22 00:54:21

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