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Information processing system with prefetch instructions having indicator bits specifying cache levels for prefetching
Information processing system with prefetch instructions having indicator bits specifying cache levels for prefetching
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机译:具有预取指令的信息处理系统,该指令具有指示符位,这些指示符位指定用于预取的缓存级别
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摘要
An information processing unit and method for controlling a cache according to a software prefetch instruction, are disclosed. Indication bits are provided for indicating a hierarchical level of a cache to which an operand data is to be transferred or a quantity of an operand data to be transferred, or both. The indication bits are provided in a software prefetch instruction such that at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction. Thus, it is not necessary to change the timing for executing a software prefetch instruction depending on which one of the caches of the hierarchical levels is hit, and a compiler can generate an instruction sequence more easily.
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