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Utopia Level 1 Utopia Level 2 Interconnection of Utopia Level 1 and Utopia Level 2
Utopia Level 1 Utopia Level 2 Interconnection of Utopia Level 1 and Utopia Level 2
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机译:乌托邦1级乌托邦2级乌托邦1级和乌托邦2级的互连
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摘要
The ATM-PHY Interface Specification There are ATM data path interface in the Utopia Level 1 and Utopia Level 2. Sometimes there is a case to match the Utopia Level 1 and Utopia Level 2. Or functional reasons of chip when the ATM data path interface is implemented as part of Utopia Level 1 There are times when you need to match the Utopia Level 1 and Utopia Level 2. In this case, it is possible to implement one FPGA IO pin number to a minimum.; This is designed for how to implement the matching of the Utopia Level 1 and Utopia Level 2 to the FPGA.
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