Method of paralleling bit serial multiplier for Galois field and a bit serial-parallel multipiler using thereof

摘要

The present invention relates to a bit serial-parallel multiplier on the Galois field which way to parallelize the bit serial multiplier on the Galois field and use them to improve the operation speed with a simple configuration.; The method of the present invention, the multiplier g [N-1: 0] on the GF (2 ^N) and converting the multiplicand x '[N-1: 0 ] of the multiplication by conversion operation result z' [N-1: 0 - a method for parallelizing the bit-serial multiplier on the Galois field and outputting, and a predetermined number of parallelism in accordance with a shift register for storing the multiplicand in parallelism depth, paralleling the combinational circuit to obtain a sum of a product of the multiplicand and the multiplier It characterized in that the predetermined number of parallelism depending on the depth of which reduces the clock number required for the operation of the multiplier improve the operation speed.; Accordingly, the present invention is the bit on the Galois field - it can be by parallelizing a serial multiplier, and can shorten the time required for the multiplier without adding much hardware, optimizing parallelism depth also the by parallelism as much as what is necessary in the system used it is possible to optimize the calculation time and hardware area.