Circuit for signal generation for reducing offset sampling time in offset compensation circuit

摘要

PURPOSE: A control signal generating circuit for reducing offset sampling time in offset compensation circuit is provided to improve an offset sampling function by reducing an influence due to a delay generated in a capacitor and an operational amplifier using a control signal. CONSTITUTION: A first switching unit(S1) switches an inner resistance(Rs) of a signal source with a non-inverting terminal of an operational amplifier(Af). A second switching unit(S2) switches the inner resistance(Rs) of the signal source with an offset capacitor(Cos) which is connected with the non-inverting terminal of the operational amplifier(Af). A third switching unit(S3) switches an inverting terminal of the operational amplifier(Af) with a node which is connected with the second switching unit(S2) and the offset capacitor(Cos). A control unit generates a control signal for controlling the first, the second, and the third switching unit(S1,S2,S3).