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Data synchronizer using a parallel handshaking pipeline wherein validity indicators generate and send acknowledgement signals to a different clock domain
Data synchronizer using a parallel handshaking pipeline wherein validity indicators generate and send acknowledgement signals to a different clock domain
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机译:使用并行握手管道的数据同步器,其中有效性指示符会生成确认信号并将其发送到不同的时钟域
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摘要
A data synchronizer transfers information across an asynchronous interface by using system domain and core domain logic on either side of the asynchronous interface. Information registers receive data beats from a data bus coupled to an external system. Each data beat is loaded into the registers in sequential order. A corresponding system valid bit is provided for each register and is set when the corresponding register is loaded. In the core domain, a corresponding set of core valid bit registers is set in response to the system valid bit registers being set. A data sampler monitors the core valid bits in sequential order and controls a multiplexor to select a corresponding one of the registers that contains valid data. The data sampler resets the core valid bits which in-turn reset the system valid bits to signal the completion of a data transfer across the asynchronous interface.
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