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Technique for forming a transistor having raised drain and source regions with a tri-layer hard mask for gate patterning
Technique for forming a transistor having raised drain and source regions with a tri-layer hard mask for gate patterning
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机译:用于形成具有凸起的漏极和源极区的晶体管的技术,该晶体管具有用于栅极构图的三层硬掩模
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摘要
By providing a hard mask layer stack including at least three different layers for patterning a gate electrode structure, constraints demanded by sophisticated lithography, as well as cap layer integrity, in a subsequent selective epitaxial growth process may be accomplished, thereby providing the potential for further device scaling of transistor devices requiring raised drain and source regions.
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