FPGA-BASED HIGH-SPEED LOW-LATENCY FLOATING POINT ACCUMULATOR AND IMPLEMENTATION METHOD THEREFOR

摘要

An FPGA-based high-speed low-latency floating point accumulator and an implementation method therefor are disclosed. The floating point accumulator of the present invention comprises a floating point adder unit, N intermediate result caches, an input control unit and an output control unit. The implementation method of floating point accumulation of the present invention divides an entire accumulative calculation process into levels, wherein different levels of accumulative calculation processes are performed in an alternating manner, and intermediate results of different levels of accumulative calculations are stored in levels; meanwhile, operation is performed completely in a streamline manner, which greatly improves utilization efficiency of an internal floating point adder, and output of a final result of the floating point accumulative calculation has low latency. The present invention improves the utilization efficiency of the floating point adders through dynamic allocation of input data of the internal floating point adder unit, thereby being capable of ensuring a high operation speed and low latency without large consumption of required logical or DSP resources.