METHOD FOR ASSISTING IN LOGIC CIRCUIT DESIGN WITH CELLS PLACED ON IC SUBSTRATE AND OPTIMIZED WIRING, DEVICE FOR ASSISTING IN LOGIC CIRCUIT DESIGN USING SAID METHOD, AND COMPUTER PROGRAM EXECUTABLE BY SAID DEVICE

摘要

PROBLEM TO BE SOLVED: To provide: a method of assisting in logic circuit design enabling placement of cells (logic operation elements) on an IC substrate and optimized wiring in a short period of time even when the logic circuit has multiple levels; a device assisting in logic circuit design using the method; and a computer program executable by this device.SOLUTION: The cells of all levels are placed in a placement area formed in a grid; and ports enabling connection to the cells in other levels are placed in a boundary portion between the placement area having the cells already placed and a placement area allowing the cells to be newly placed therein. A cell and another cell are wired for the cells in the same level, and a cell and a port are wired for the cells in different levels, such that the sum total of the wiring lengths is minimized.