Peek/poke interface on radio system core engine modem to allow debug during system integration

摘要

A system and method for allowing individual register access during system integration and test is disclosed. A Chip select is routed between an OMAP processor and a waveform FPGA and configured to allow individual register access during system integration and test. Logic is then added to the FPGA to support the single access to the FPGA's peripherals. This allows the user connected to the debug port to be able to send and receive individual commands to and from the waveform FPGA's peripherals. A Graphical User Interface (GUI) maybe developed to provide a graphical interface or scripts may be used to assemble multiple commands thereby increasing flexibility to configure the peripherals during integration and troubleshooting.