首页>
外国专利>
ARCHITECTURE AND DESIGN AUTOMATION OF HIGH PERFORMANCE LARGE ADDERS AND COUNTERS ON FPGA THROUGH CONSTRAINED PLACEMENT
ARCHITECTURE AND DESIGN AUTOMATION OF HIGH PERFORMANCE LARGE ADDERS AND COUNTERS ON FPGA THROUGH CONSTRAINED PLACEMENT
展开▼
机译:通过约束放置在FPGA上的高性能大型添加器和计数器的体系结构和设计自动化
展开▼
页面导航
摘要
著录项
相似文献
摘要
Technologies are described to automate design of field programmable gate array (FPGA) circuits, specifically for fast and efficient architectures for large integer adders and counters through direct instantiation of carry chain primitives and lookup tables in circuit description. In some examples, placement of circuits on relatively adjacent slices may be controlled such that the slices are strongly and logically coupled to enable compact placement and thereby contributing to reduced routing delay and FPGA chip area. Design descriptions and constraint files may be automatically generated by a design application providing operand-width scalability with respect to operating frequency of the designed circuit.
展开▼