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机译:A High-Speed Low-Power Multi-VDD CMOS/SIMOX SRAM With LV-TTL Level Input/Output Pins—Write/Read Assist Techniques for 1-V Operated Memory Cells
authorLink("Shibata, N.");
CMOS; LV-TTL; SIMOX; SRAM; current sense; fully depleted SOI; high speed; low power; multi-VDD; segmented bitline; squashed memory cell; switched powerline impedance;