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机译:A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea;
Qualcomm Inc., San Diego, CA, USA;
Thermal noise; Jitter; Phase locked loops; Bandwidth; Oscillators; Dynamic range; Silicon;