SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor

摘要

The SPARC M7 processor offers up to 3 the throughput performance of Oracle's previous SPARC processor generation for many enterprise workloads. It contains 32 highly optimized S4 cores that include a more efficient L2 cache scheme, support for VIS extensions, virtual address masking, and user-level synchronization instructions to provide substantial single thread performance over the predecessor design. A total of 256 threads per chip provide the throughput performance required by even the most demanding enterprise applications. Both throughput and single thread performance benefit from a large fully shared 64 MB on-chip L3 cache with very low latency. The 0.5 TB/s on-chip communications bandwidth requirements are served via a semi-custom on-chip network (OCN) in place of the traditional crossbar. Hardware database analytics accelerator units (DAX) achieve up to 10x the performance for in-memory database queries, include decompression and messaging operations, and support pointer version checking for securing application data through application data integrity (ADI), as well as fine grained memory migration. The SerDes IO operate up to 18 Gbps, offering 1 TB/s total bandwidth for memory and multi-socket interfaces. New on-chip power management features include fast and accurate dynamic power meters, thermal sensors, and a fine-grain thermal, current, and chip power control engine to enable maximum performance/Watt. Special circuits like the voltage shift module (VSM) were developed to cope with the clock and voltage domain crossing issues, while the asymmetric frequency lock loop (AFLL) main clock generation circuit also provides Ldi/dt droop compensation leading to substantial power savings.