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机译:340 mV–1.1 V,289 Gbps / W,2090门NanoAES硬件加速器,具有在22 nm Tri-Gate CMOS中进行面积优化的加密/解密GF(2 4)2多项式
Circuit Research Lab, Intel Corporation, Hillsboro, OR, USA;
Encryption; Hardware; Logic gates; Polynomials; Registers; Throughput; Advanced encryption standard; composite-field polynomial arithmetic; encryption hardware accelerator; lightweight crypto; on-the-fly key-generation; security; ultra-low power AES;
机译:在22 nm三门CMOS中提供340 mV至0.9 V 20.2 Tb / s的源同步混合数据包/电路交换16×16片上网络
机译:280 mV至1.1 V 256b可重配置SIMD矢量置换引擎,在22 nm Tri-Gate CMOS中具有二维混洗
机译:用于45 nm高性能微处理器的内容保护的53 Gbps本机复合场AES加密/解密加速器
机译:340mV–1.1V,289Gbps / W,2090门NanoAES硬件加速器,具有区域优化的加密/解密GF(2 4 sup>) 2 sup>多项式,位于22nm三栅CMOS中