Design of Low-Gate-Count Low-Power Microprocessors with High Code Density for Deeply Embedded Applications

摘要

Deeply embedded applications demand small area, low power, high code density, and low design complexity for high adaptability. Both a 16-bit microprocessor with a 4G byte linear memory space and a 4-bit processor are proposed and designed to achieve these goals. Hardware reuse and sharing, multicycle architecture, compact instruction set architecture, and counter-based instruction decoder are utilized to reduce gate count. As a result, gate count and power dissipation of the synthesized ASIC gate-level netlists of 16-bit and 4-bit processors are less than 14,000, 1,490, 0.5m W, and 0.06m W, respectively, at 10MHz in a 0.18 mu m digital CMOS technology. The proposed 16-bit and 32-bit processors are extendable instruction set computers whose high code density is demonstrated to reduce code bytes by 40% over a reduced instruction set computer. The pipelined EISC processor only consumes 50 mu W/MHz with 10,800 gates in a 0.18 mu m CMOS process.