A 3V Low Power 156/622/1244 Mbps CMOS Parallel Clock and Data Recovery Circuit for Optical Communications

摘要

This paper presents the implementaton of a 3V low power multi-rate of 156, and 1244 Mbps clock and data recovery circuit (CDR) for optical communications tranceiver us- ing new parallel clock recovery architecture based on dual charge- pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical system uses the method that compares the input data with recovered clock, the proposed circuit compares a 1/2-bit de- layed input data with the serial data generated by the recovered eight-phase clock signals.