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首页> 外文期刊>Signal Processing, IEEE Transactions on >A Hybrid RF/Baseband Precoding Processor Based on Parallel-Index-Selection Matrix-Inversion-Bypass Simultaneous Orthogonal Matching Pursuit for Millimeter Wave MIMO Systems
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A Hybrid RF/Baseband Precoding Processor Based on Parallel-Index-Selection Matrix-Inversion-Bypass Simultaneous Orthogonal Matching Pursuit for Millimeter Wave MIMO Systems

机译:基于并行索引选择矩阵求逆旁路同时正交匹配追踪的毫米波MIMO系统混合RF /基带预编码处理器

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摘要

A millimeter wave (mm-wave) communication system provides multi-Gb/s data rates in short-distance transmission. Because millimeter waves have short wavelength, transceivers can be composed of large antenna arrays to alleviate severe signal attenuation. Furthermore, the link performance can be improved by adopting precoding technology in multiple data stream transmission. However, the complexity of radio frequency (RF) chains increases when large antenna arrays are used in mm-wave systems. To reduce the hardware cost, the precoding circuit can be jointly designed in both analog and digital domains to reduce the required number of RF chains. This paper proposes a new method of building the joint RF and baseband precoder that reduces the computation complexity of the original precoder reconstruction algorithm and enables highly parallel hardware architecture. Moreover, the proposed precoder reconstruction algorithm was designed and implemented using TSMC 90-nm UTM CMOS technology. The proposed precoder reconstruction processor supports the transmissions of one to four data streams for 88 mm-wave multiple-input multiple-output systems. The operating frequency of this chip was 167 MHz, and the power consumption was 243.2 mW when the supply voltage was 1 V. The core area of the postlayout result was about 3.94 mm. The proposed processor achieved 4, 4.9, 6.7, and 6.7 M channel matrices per second in four-, three-, two-, and one-stream modes, respectively.
机译:毫米波(mm-wave)通信系统在短距离传输中提供了Gb / s的数据速率。因为毫米波具有短波长,所以收发器可以由大型天线阵列组成,以减轻严重的信号衰减。此外,在多数据流传输中采用预编码技术可以提高链路性能。但是,在毫米波系统中使用大型天线阵列时,射频(RF)链的复杂性会增加。为了降低硬件成本,可以在模拟和数字域中共同设计预编码电路,以减少所需的RF链数量。本文提出了一种构建联合RF和基带预编码器的新方法,该方法可降低原始预编码器重构算法的计算复杂度,并实现高度并行的硬件体系结构。此外,本文提出的预编码器重构算法是采用台积电90纳米UTM CMOS技术设计和实现的。所提出的预编码器重构处理器支持88毫米波多输入多输出系统的一到四个数据流的传输。该芯片的工作频率为167 MHz,电源电压为1 V时功耗为243.2 mW。后布局结果的核心面积约为3.94 mm。拟议的处理器分别在四流,三流,两流和一流模式下实现了每秒4、4.9、6.7和6.7 M的信道矩阵。

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