BUS MATRIX SYNTHESIS BASED ON STEINER GRAPHS FOR POWER EFFICIENT SYSTEM ON CHIP COMMUNICATIONS

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BUS MATRIX SYNTHESIS BASED ON STEINER GRAPHS FOR POWER EFFICIENT SYSTEM ON CHIP COMMUNICATIONS

机译：基于斯蒂纳图的总线矩阵综合在高效电力通信系统中的应用

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Power consumption of system level on chip communications is becoming more significant in the overall system on chip power as technology scales down. High bandwidth is desired to enhance parallelism for better performance, and the power efficiency on this

机译：随着技术的缩减，片上通信的系统级功耗在整个片上系统功耗中变得越来越重要。需要高带宽来增强并行性以获得更好的性能，并为此提高功率效率

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《International Journal of Engineering Trends and Technology》 |2011年第2期|共页
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1. Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications [J] . Wang R., Zhang Y., Chou N.-C., Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2011,第2期

机译：基于Steiner图的总线矩阵综合，可实现节能的片上系统通信
2. CAPPS: A Framework for Power–Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis [J] . Pasricha S., Park Y.-H., Kurdahi F. J., Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2010,第2期

机译：CAPPS：基于总线矩阵的片上通信体系结构综合中的功率-性能折衷的框架
3. Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic [J] . Liu L.-C.E., Sechen C. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 1999,第10期

机译：使用基于图的高效Steiner树启发式算法进行多层芯片级全局路由
4. Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications [C] . Renshen Wang, Nan-Chi Chou, Bill Salefski, Proceedings of the 46th Annual Design Automation Conference . 2009

机译：使用最短路径Steiner图进行片上系统通信的低功率门控总线综合
5. A Scalable and Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band [D] . Saxena, Sagar. 2017

机译：在太赫兹频段中提供了一种可扩展且节能的石墨烯基互连框架，包括芯片内和芯片间无线通信
6. The System Power Control Unit Based on the On-Chip Wireless Communication System [O] . Tiefeng Li, Caiwen Ma, WenHua Li 2013

机译：基于片上无线通信系统的系统电源控制单元
7. BUS MATRIX SYNTHESIS BASED ON STEINER GRAPHS FOR POWER EFFICIENT SYSTEM ON CHIP COMMUNICATIONS [O] . 2015

机译：基于steiner图的总线矩阵综合在芯片通信中的功率效率系统

BUS MATRIX SYNTHESIS BASED ON STEINER GRAPHS FOR POWER EFFICIENT SYSTEM ON CHIP COMMUNICATIONS

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