Automatic topology selection and sizing of class-D loop-filters for minimizing distortion based on an evolutionary optimization kernel

摘要

This paper presents an optimization methodology for continuous time loop-filters design applied to Class-D amplifiers. The methodology is based on an evolutionary optimization approach which integrates both the topology selection and circuit sizing by automatically generating optimal sized topologies and performance tradeoffs for the Class-D amplifier. The presented approach is demonstrated on two cases: for the design of a half-bridge amplifier and for a fully differential BTL class-D loop filter topology that achieves less than 0.003% THD at 680 mW output power in typical 0.18 μm CMOS technology.