频率计权网络的数字电路实现

摘要

An implementation scheme of digital circuit for frequency weighting network is presented. The frequency weighting filter generated by the filter design tool is described in detail,which is converted into transplantable and synthesizable HDL code by using HDL code generation tool,and can be implemented on FPGA. The test process of the filter model was simulated and verified respectively by software and hardware. The test results show that the designed frequency weighting network conforms to weighting characteristic and tolerance standard,and can simplify circuit structure and operation,reduce power consumption and the cost,save resources and improve efficiency. The frequency weighting value of the signal can be obtained quickly.%提出一种频率计权网络的数字电路实现方案，详细阐述由滤波器设计工具生成频率计权滤波器，然后采用HDL代码生成工具将其转换成可移植、可综合的能在FPGA上实现的HDL代码，分别在软件和硬件上进行仿真验证测试的过程。结果表明，设计的频率计权网络符合计权特性及允差标准，且采用此方法设计的频率计权网络简化了电路结构，操作简单，降低了功耗、成本，节省了资源，提高了效率，能快速得出信号的频率计权值。