四阶Sigma-Delta微加速度计系统设计与分析

摘要

System level analysis and design of a single-loop fourth-order sigma-delta（ΣΔ） accelerometer is presented to reduce quantization noise and enhance resolution of the micromachined accelerometer.Stability of the system is analyzed by root locus method based on the linear model established in this work.Theoretical analysis indicates that the forth-order ΣΔ micromachined accelerometer has good performance in noise,dead zone and idle tone.Based on the analysis and discussion of the system level,the transistor level design of the interface circuit is implemented,the circuit is fabricated in 0.5 μm two poly two metal CMOS process,and the tested results indicate that the sensitivity is 1.2 V/g,nonlinearity is 0.2%,open-loop noise density is 12 μg/Hz1/2,closed-loop noise density is 80 ug/Hz1/2 and the power dissipation is 40 mW.%为了降低Sigma-Delta（ΣΔ）微机械加速度计量化噪声,提高系统分辨率,完成了一种单环四阶ΣΔ微加速度计的分析与设计,建立了系统的线性模型,并在此基础上,采用根轨迹法分析了系统稳定性.理论分析表明所建立的四阶ΣΔ微加速度计系统在噪声特性、死区、空闲音方面都具有优良的特性.在系统级的分析与讨论基础上,实现了传感器接口电路晶体管级的设计,该电路采用0.5μm 2层多晶2层金属CMOS工艺流片,系统测试结果表明该加速度计灵敏度为1.2 V/g,非线性度为0.2%,开环噪声密度12μg/Hz1/2,闭环噪声