A novel test approach for interconnect resources (IRs) in field programmable gate arrays (FPGA) has been proposed.In the test approach,SBs (switch boxes) of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks (CLBs) in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip (SoC) hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.
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机译:Field programmable gate array implementation of an adaptive filtering based noise reduction and enhanced compression technique for healthcare applications
机译:伽玛辐射效果测试的要求:28A003A(REV 0)PMOS电源开关(环境 - 动态)28A004A(REV 0)PMOS电源开关(LN $ SUB 2 $dynamic Test 28a003b(Rev 0)PMOS NOR GATE(环境动态)测试28A004B(REV 0)PMOS NOR GATE(LN $ SUB 2 $ -dynamic)