小数乘法器的低功耗设计与实现

摘要

A low-power design methodology is presented for decimal multiplier,the methodology optimization object is the width of the adders in synthesized multiplier.The methodology resolves the problem of optimization logic joining into optimized system existed in present lowpower design.It can reduce system power and area significantly without additional logic,and the system working efficiency and calculation accuracy are remained.After optimizing a radiofrequency circuit using the proposed method,FPGA test result shows that logic utilization is reduced by 17.9％,total registers number is reduced by 30.7％,and total block memory bits utilization is reduced by 21.5％.The methodology perform well in the system optimization,including the optimization of large-scale multipliers.%提出一种针对小数乘法器的低功耗设计算法,其优化指标为综合后小数乘法器内部寄存中间运算结果的寄存器位宽,解决了目前低功耗设计中算法自身逻辑单元被引入系统从而降低系统优化效果的问题.该算法能够在不降低系统工作效率、不损失系统运算精度、不增加额外逻辑单元的条件下,大幅降低系统功耗和面积.在使用该算法对某一射频模块进行优化后,硬件测试结果显示该射频模块对某型号FPGA的逻辑占用率相比优化前降低17.9％,寄存器总数降低30.7％,存储单元占用率降低21.5％.该算法适用于对含有大量小数乘法运算的系统进行低功耗优化.