高k介质电导增强SOI LDMOS机理与优化设计

摘要

A high-k dielectric conduction enhancement SOI LDMOS is proposed and investigated by simulation. The high-k dielectric pillars are located at sidewalls of the drift region. The high-k dielectric assists the self-adapted depletion in the drift region, reshapes the electric field distribution, and makes the three-dimensional RESURF effect realized in a high-voltage blocking state. Dependences of the breakdown voltage (VB) and the specific on-resistance (Ron,sp) on device parameters are exhibited using three-dimensional simulation. Simulation results show that the proposed structure increases VB by 16%-18% and decreases Ron.sp by 13%-20%, compared with the conventional super-junction SOI LDMOS. Furthermore, the charge-imbalance caused by the substrate-assisted depletion effect is alleviated.%本文提出一种高k 介质电导增强SOI LDMOS 新结构(HK CE SOI LDMOS)，并研究其机理。 HK CE SOI LDMOS的特征是在漂移区两侧引入高k介质，反向阻断时，高k介质对漂移区进行自适应辅助耗尽，实现漂移区三维RESURF效应并调制电场，因而提高器件耐压和漂移区浓度并降低导通电阻。借助三维仿真研究耐压、比导通电阻与器件结构参数之间的关系。结果表明， HK CE SOI LDMOS与常规超结SOI LDMOS相比，耐压提高16%-18%，同时比导通电阻降低13%-20%，且缓解了由衬底辅助耗尽效应带来的电荷非平衡问题。