Exploration and augmentation of delay-insensitive asynchronous circuits operating in subthreshold regime.

摘要

The demand for energy-efficient systems has pushed integrated circuit designers to rethink multiple aspects of a system including the necessity of a large clock tree, realistic performance specifications, and even the source of energy delivered. Subthreshold circuits have been shown to be the solution to systems with a performance less than 100MHz with asynchronous solutions providing even better energy consumption. The work in this thesis provides circuit augmentations to control leakage energy through body biasing and performance scaling at a constant supply voltage. An asynchronous Intel 8051 ALU is fabricated using the IBM 8RF-LM 0.13 mum process with results down to VDD=0.1 V.