The masking of gate level detail is both the blessing and the curse of the behavioral VLSI synthesis paradigm. Abstraction is a blessing because efficient design exploration is enabled, but it is a curse because gate level information necessary for various optimizations, including testability, is not available. To address testability effectively, a synthesis technique is required which integrates analysis at the behavioral level to ensure efficiency and at the gate level to ensure accuracy. Behavioral testability problems, which are independent of gate level detail, must be identified to enable efficient testable design space exploration. At the same time, critical gate level testability information must be identified to address particularly hard to test faults which cannot be categorized behaviorally.; This dissertation investigates behavioral synthesis for built-in self-test (BIST) using behavioral analysis to improve overall testability, and critical gate level analysis to target pseudo-random resistance problems associated with BIST. Estimation metrics are developed to estimate behavioral testability problems including test concurrency and reconvergent fanout. An efficient gate level fault coverage estimate is also developed using component-specific hard-to-test fault information together with behavioral simulation. A behavioral synthesis system is presented which uses the behavioral and gate level testability metrics to improve the testability of the overall design, and the hard-to-test faults in particular. The identification and optimization of the behavioral test problems presented, pioneers testability consideration during behavioral synthesis. The use of component-specific gate-level information enables test problems to be addressed with accuracy never before possible during behavioral synthesis. The growing needs for both complexity management and detailed fault targeting are mutually addressed through the merged use of behavioral and component-specific information during test synthesis.
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