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An automatic test generation system for testing virtual memory operations.

机译:用于测试虚拟内存操作的自动测试生成系统。

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As general purpose processors become increasingly complex, the task of testing them also becomes more difficult. Because of the tremendous verification space presented by a processor, numerous test cases are needed to sufficiently exercise the processor. An automatic test generation system is a software tool embedded with the knowledge of the processor instruction set and behavior. It generates tests which can run on either a simulation model or the actual processor chip. The goals of the system are to provide a large bandwidth of test cases and, in doing so, cover as much of the verification space as possible. A large bandwidth of tests is achieved by automating the test generation task. The functional coverage of these tests is maximized by employing pseudo-random generation of interacting instruction sequences. Because test execution is still the primary method of testing processors at the chip level, automatic test generation systems are heavily relied upon in industry. However, existing automatic test generation systems do not significantly cover the virtual memory operations.; For several generations of general purpose processors, virtual memory support has been a necessary feature. But it usually remains largely untested until the processor is robust enough to boot up an operating system. Even then the processor may still contain many errors related to its virtual memory operations. In order to test virtual memory operations earlier in the design cycle and provide more coverage, automatic test generation systems must overcome some problems. This dissertation presents these problems and describes the design and implementation of an automatic test generation system that thoroughly covers the virtual memory operations of a pipelined superscalar commercial processor. The problems and solutions are general and apply to all general purpose processors, including Reduced Instruction Set Computers (RISC's), although the system was designed to test an X86 processor.
机译:随着通用处理器变得越来越复杂,测试它们的任务也变得更加困难。由于处理器提供了巨大的验证空间,因此需要大量测试用例才能充分利用处理器。自动测试生成系统是一种嵌入了处理器指令集和行为知识的软件工具。它生成可以在仿真模型或实际处理器芯片上运行的测试。该系统的目标是提供大量的测试用例,并以此覆盖尽可能多的验证空间。通过自动执行测试生成任务,可以实现较大的测试带宽。通过使用交互指令序列的伪随机生成,可以最大限度地提高这些测试的功能覆盖范围。由于测试执行仍然是在芯片级别测试处理器的主要方法,因此在工业上高度依赖自动测试生成系统。但是,现有的自动测试生成系统并未充分涵盖虚拟内存操作。对于几代通用处理器,虚拟内存支持已成为必需的功能。但是它通常在很大程度上未经测试,直到处理器足够强大以启动操作系统为止。即使这样,处理器仍可能包含许多与其虚拟内存操作有关的错误。为了在设计周期的早期测试虚拟内存操作并提供更大的覆盖范围,自动测试生成系统必须克服一些问题。本文提出了这些问题,并描述了自动测试生成系统的设计和实现,该系统彻底涵盖了流水线式超标量商用处理器的虚拟内存操作。问题和解决方案很普遍,并且适用于所有通用处理器,包括精简指令集计算机(RISC),尽管该系统旨在测试X86处理器。

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