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FPGA implementation of HDCP encryption and decryption on partial frame.

机译:HDCP在部分帧上进行加密和解密的FPGA实现。

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摘要

Digital Visual Interface (DVI) is gradually being applied to high quality and high resolution digital video signal transfer between graphic controller and digital display. There have been widespread applications of DVI interface. The valuable digital content, however, is vulnerable to unauthorized access during the transmission. Image /video protection become serious issues in current data transmission. The software implementation in image encryption is more competitive in flexibility and portability but may not meet some timing constraints. DVI transmission is real-time and has high-speed demand, hardware implementation of HDCP encryption is presented here and operate on a partial frame.;HDCP served as stream cipher is used to protect the signal from illegal copying or propagating specifically through DVI. My design work is to perform HDCP encryption/decryption on a partial frame in real-time transmission. The selected area is defined by some special pixels. Unauthorized receiver without keys can not access to the legible content in selected area of image/video. In this way, the owner of content could prevent illegal copy or eavesdrop by perform encryption on defined area.;This thesis presents research into a high speed FPGA implementation of HDCP Encryption and Decryption on partial frame. The application works in the following manner. The image is to be encrypted in software using Matlab and transferred to the FPGA, and then encrypted image will be decrypted in hardware in that machine. The target of this thesis is to demonstrate the feasibility of HDCP encryption/decryption on partial frame in PC through DVI interface and make performance comparison between hardware and software implementation.;Our work-steps includes Paper Designing, Writing VHDL Code, Simulating the code on " ModelSim XE 6.4b ", Synthesizing & Implementing (i.e. Translate, Map & Place and Route) the code on "Xilinx - Project Navigator, ISE 11 " with Chip XC3SD3400A of Spartan-3A DSP 3400A & XST Synthesis Tool.
机译:数字视频接口(DVI)逐渐应用于图形控制器和数字显示器之间的高质量和高分辨率数字视频信号传输。 DVI接口已经得到了广泛的应用。然而,有价值的数字内容在传输过程中容易受到未经授权的访问。图像/视频保护成为当前数据传输中的严重问题。图像加密中的软件实现在灵活性和可移植性方面更具竞争力,但可能无法满足某些时序约束。 DVI传输是实时的且具有高速需求,此处介绍了HDCP加密的硬件实现并在部分帧上运行。HDCP用作流密码,用于保护信号免于通过DVI专门复制或传播。我的设计工作是在实时传输中对部分帧执行HDCP加密/解密。所选区域由一些特殊像素定义。未经授权的无钥匙接收者无法访问图像/视频所选区域中的清晰内容。这样,内容所有者就可以通过在定义的区域上执行加密来防止非法复制或窃听。;本文对在部分帧上HDCP加密和解密的高速FPGA实现进行了研究。该应用程序以以下方式工作。该图像将使用Matlab在软件中进行加密并传输到FPGA,然后加密的图像将在该计算机的硬件中解密。本文的目的是通过DVI接口论证在PC机上进行部分帧HDCP加密/解密的可行性,并在硬件和软件实现之间进行性能比较。 “ ModelSim XE 6.4b”,使用Spartan-3A DSP 3400A和XST综合工具的XC3SD3400A芯片,在“ Xilinx-Project Navigator,ISE 11”上合成和实现代码(即翻译,地图,放置和布线)。

著录项

  • 作者

    Hou, Yuang.;

  • 作者单位

    State University of New York at Binghamton.;

  • 授予单位 State University of New York at Binghamton.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.S.
  • 年度 2010
  • 页码 67 p.
  • 总页数 67
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 水产、渔业;
  • 关键词

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