A high-performance low-power nanophotonic on-chip network

摘要

On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfer, limits the power efficiency and performance scalability of many-core chip-multiprocessor systems. This article presents Iris, a CMOS-compatible high-performance low-power nanophotonic on-chip network. Iris' linear-waveguide-based throughput-optimized circuit-switched subnetwork supports throughput-sensitive data transfer. Iris' planar-waveguide-based WDM broadcast-multicast subnetwork optimizes latency-critical traffic and supports the circuit setup of circuit-switched communication. Overall, the proposed design delivers an on-chip communication backplane with high power efficiency, low latency, and excellent throughput.