The opportunity cost of low power design

摘要

The time-to-market pressures combined with the immense power reduction design space of VLSI design call for an evaluation of power savings opportunities prior to the investment in design effort. This paper presents an estimation methodology for predicting the power savings of circuit tuning for an industrial chip design project. A comparison between the estimated and actual power savings realized through tuning over 100 macros on the chip validates the accuracy of this estimation methodology.