An optimization strategy for low energy and high performance for the on-chip interconnect signalling

摘要

Coupling capacitance between adjacent wires in on-chip interconnect significantly increases the average transition energy dissipation, and the maximum delay. This paper proposed a novel encoding scheme to, further, reduce the coupling energy dissipation, and delay. Specifically for 65nm CMOS technology, we present an 8-bit to 10-bit equivalent solution that reduces the energy dissipation by 55%, and delay by 24%, without any additional area penalty, while requiring a less complex circuit overhead when compared with transition pattern coding (TPC) scheme.