Design of CMOS Based 1-bit Comparator with MTCMOS and Forced Stack Technique in 180nm Technology

摘要

Leakage power and propagation delay have adverse effects on the working of CMOS(nanometer) technology-based logic circuits. The motivation behind this research work is to cut down the leakage power dissipation and propagation delay, the major influencing parameters in logic circuits. The proposed work is on one-bit comparator which uses Multi threshold technique (MTCMOS), stacking technique and gate minimising logic. The technology used is l80ηm and voltage used is 1.8V. The work is performed and analyzed in SPICE. The new circuit has improved performance in power dissipation as well as propagation delay. The modified circuit shows power dissipation of 48.12p W and delay of 330pS. Comparison with previously reported circuit shows advantage of low power and less delay.