Design of moore finite state machine with extended state codes

摘要

The new method is proposed for reduction of chip area occupied by logic circuit of Moore FSM implemented with PLAs. It is based on the representation of the state code as a concatenation of the code of class of pseudoequivalent states and code of state inside this class. Such an approach allows elimination of dependence among states and output variables. It allows the hardware reduction in the FSM logic circuit in comparison with known design methods.